▶ DDR3 Bandwidth with less than half the signals and using less than 10% of the PCB area.
▶ World’s 1st DRAM in Wafer Level CSP(WLCSP)
• The smallest and least expensive package option
▶ DDR3 derivative architecture offered in BGA,
Bare Die(KGD) and WLCSP
• Capacity from 256Mb
▶ AEC-Q100 Grade 2 Qualified